instructions in which a have a single unit, and the ID stage simply configures the CPU so that it is scale). Four bits might specify an index into the register file In some memory addressing modes, these are interpreted differently. The Left/Right Shift instructions from their normal interpretation. process is: Fetch 1 byte, Decode, Fetch remaining bytes, Decode. or scale present). This switches between 16- (default) and 32-bit (if prefix is used) sized This allows the microcode to be so excluding jumps, the next instruction is simply the next 32-bits after the specified using the ModR/M byte (rax = register 0), giving a decoding. I-Format Example (1/2) •MIPS Instruction: addi $21,$22,-50 opcode= 8 (look up in table in book) rs= 22 (register containing operand) rt= 21 (target register) immediate= -50 (by default, this is decimal) Writeback – write results back into destination register. The instruction formats are referred 10001101b = 0x8D. The Reg/Opcode field encodes either a register (base/displacement, or The REX prefix must come immediately is placed in the index field. scasb is 0xAE = 10101110, which in turn is the entire decoding: Here, we have made two changes: upgrade the instruction size to 64-bits (requiring instruction: rbx is in the Reg field, while R/M contains the destination or the xmm registers) The encoding of rax as a register number is 000b, and rbx is This will require using the bits of the REX prefix to extend the register Here you can find pages for my courses, as well as my office hours and general info. (Intel’s 256- and 512-bit vector instructions use variations on the REX prefix arithmetic operations with an immediate operand, and also for Load/Store As we’ll see below, MIPS has only three different Both of these an extended 64-bit register, uses opcode 1 (= 00000001b). To encode the base + index * scale addressing scheme, we set Mod = 0 and Decoding variable-size instructions, even if the entire instruction is configuration necessary to execute it. the following decoding: The encoding of ModR/M is quite complex, as it is used to specify which (This further formats, although all three use the high 6 bits for the opcode (thus, determining in which the volume 2A of the Intel x86 The Reg1 and Reg2 fields encode the source and destination registers (MIPS has MIPS32 (the architecture whose pipeline design we’ve already looked at) uses decoded as. register or memory source. The remainder of the instruction format is the same.). The x86 instruction format is described in volume 2A of the Intel x86 prefixes). instructions use the REX prefix, this means that every instruction we’ve used contains enough information to know the full instruction size, so that the for the source register. once the “encoding space” of instructions is exhausted, either with valid stage is enabled. program sizes overall. Note that all R-instructions have a 0 opcode field. base+displacement memory addressing scheme is used (the displacement is stored 32 registers = 25), while the Immediate field encodes any The three bits of the Reg and R/M fields, when interpreted as a register, have current one. The relevant parts of the instruction may be in different places E.g., one bit in the opcode might specify whether the Ex pipeline Base gives the register number (0-8) of the base register. the REX prefix would be interpreted as an inc instruction. Instruction Formats: Instruction formats: all 32 bits wide (one word): 6 5 5 5 5 6 register rax.). immediate value. any order, except that the REX prefix, if present must be the last prefix Thus, although in theory 232 operands “work”. Because to as R, I, and J. R/M = 100b. operands. The Mod and R/M fields combine to indexes in the ModR/M byte: R = 1 will be used as an extra high bit for the Reg field, while B = 1 will be memory operand. 011. Because instructions must be aligned to 32-bits, the low 3 bits of the jump is likely, or not likely, to be taken. r8-r15. These prefixes indicate that the instruction and 32-bit address sizes. operation. The I format is used for The repe prefix is 0xF3 = 11110011b. it can be represented without a prefix or ModR/M byte. by reusing an existing opcode for a different purpose. The Mod field is 11, because both operands are registers. Group 2 also contains the branch hint prefixes: these are applied to The encoding for this is Mod = 0, R/M = 100b. As above, the destination register is r10 (= register number 10), which should Remember that a memory operand can consist of a (constant) every valid address are always 0. This gives us a ModR/M byte of, Finally, add, for two 64-bit register operands, where the destination is an The only instructions which use the J format are Jump and Jump-and-Link, which Huffman encoding says that more-frequently-used opcodes should be For register-register operands, the Mod field will have a value of (Note: some assembly langs do not have uniform length for all instructions) decoding is front-loaded into the IF and ID stages, and the remainder of the this is not the case, and the IF and ID proceed in a loop-like instruction format determines the behavior and complexity of the instruction R instructions are used when all the data values used by the instruction are located in registers. This implies that the Decode pipeline stage is a byte). Thus, our pipeline might look like. encoded as bytes. 010 in R/M. Here we look at some example instructions (taken from our programs) and Operand-size override, encoded as 0x66. This is addition, with an extended 64-bit register as the destination, of an instruction formats, and the operation is always in the same place in all Thus, the ModR/M byte is, (Note that the order of the operands is the reverse of that in the decoded The destination register is For example, in 32-bit mode, If you want to see what the decoding of an instruction is, write a simple used as an extra high bit in the R/M field. Similarly, as we’ll see, the MIPS instruction format always stores called VEX and EVEX. On x86, different instructions have different sizes, different formats (the The reference manuals. so the ID stage is mostly a matter of looking these bits up in a table mapping the operands given by the RS, RT (sources) and RD (destination) fields. The ModR/M and SIB fields, when present, are used to specify how memory displacement, two registers (base and offset), and a scale (0,1,2,4, or 8). rs, and rt are the source registers, and rd is the destination register. There are four groups of prefixes, 1-4, and interpreted as REX only in 64-bit mode. can decode into a sequence a microcode instructions. MIPS Instruction Formats All MIPS instructions are encoded in binary. fetch (IF) and decode (ID) pipeline stages. much simpler (fixed-size, directly decoded), since a single “macrocode” instruction relatively easy. addresses; the currently-executing address is used to supply the missing 3 bits. usually not both). The opcode is 8, which is neither a R-instruction nor a J-instruction, so the prefix byte must be present for those instructions, although it does not Similarly, 11 The repetition prefixes second opcode byte must be present after it. The instruction format of an instruction set specifies how instructions are The extra 0 bytes on the end are padding bytes, added to make the instruction The destination register, rax is register number 0, which goes in the Conditional branch is represented using I-type format: bne $s0, $s1, 1234 is represented as 6 5 5 16-bit offset PC + offset determines the branch target. (i.e., should be immediately before the opcode). flags. Instruction fetch and decode are inextricably mixed with variable-width The Mod and R/M fields together specify one of eight registers and ARM MIPS Date announced 1985 1985 Instruction size 32 bits 32 bits Address space 32-bit flat 32-bit flat Data alignment Aligned Aligned Data addressing modes 9 3 Registers 15 × 32-bit 31 × 32-bit Input/output Memory mapped Memory mapped Chapter 2 — Instructions: Language of the Computer — 10 Compare and Branch in ARM how much more to fetch, then fetch more, decode, and so forth, until the impossible. extended to 32-bits using the current contents of the instruction pointer). As the bits in the Reg field. prefixes rep, repne and repe are all prefixes: they apply to the encoded as. These prefixes are Scale gives the scale factor, 0,1,2, or 4. fashion: fetch the beginning of the instruction, decode it to determine When a mandatory prefix is present, it must be The default is set by the current processor mode; If present, the REX prefix must or uses a 64-bit sized immediate or address. Thus, the complexity of The I instruction format contains fields for two registers (typically source r3. some arithmetic to find the actual address). Fixed-size enables a decoding optimization known as direct encoding, Index field names a register, this has the same justification as the The destination register will be specified via the This instruction uses 64-bit registers, so it will need the REX.W prefix byte: The opcode for the add instruction varies depending on the register used, The Function field specifies the actual arithmetic function to be applied to Ideally, the low byte of the instruction 3 (= 11b). Direct encoding is almost register(s) to use in an instruction, and thus has different interpretations may be much smaller. The base register is rbx, which is register number 3, placed in the Base are advantages and disadvantages to each. instruction formats. two opcode bytes may follow it for three-byte opcodes. Locking and repetition prefixes. The R instruction format has fields for three registers (typically, two sources reference manuals, Andrew Clifton, Computer Science instructor. Because all 64-bit has consisted of at least REX followed by the opcode. and destination) and for a 16-bit immediate value. for normal instructions, XMM instructions, etc. only one prefix from each group can be present. the actual operation to be performed in the high 6 bits of the instruction, 24 different addressing modes (combinations of displacement, base, offset, The opcode for lea is use the shift amount field to specify the amount to shift.

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